FIGS. 1 and 2A-F illustrate a prior art inter-metal dielectric process for forming multilevel metal structures on an semiconductor IC 10. Such multilevel metal structures may be used, for instance to interconnect several commonly connected devices incorporated in the semiconductor IC 10 such as sources and/or drains of MOS devices. In FIG. 1, first metal I regions 18, 19 of a MOS device 310 are formed, in a conventional manner to be described below. Illustratively, the MOS device 310 is formed in a P-well region 312 of an N-type silicon substrate. N+-type source and drain regions 314 and 316 are formed in the P-well 312. Field oxide (FOX) regions 315, 317 which are relatively thick oxide regions separate the device 310 from adjacent devices formed on the substrate. The gate 318 is made from polysilicon. The gate 318 is separated from the P-well surface by the thin gate oxide 319 and is enclosed by the dielectric 320 which also may be oxide. The device 310 is covered by a pre-metal dielectric layer 330. The layer 330 is illustratively a dual stack of TEOS (Tetraethylorthosilicate) based USG/BPSG (undoped silicon glass/borophosphosilicate glass) with a thickness of 3000-5000 Angstroms. The layer 330 is formed by liquid phase chemical vapor deposition in a vertical furnace.
The metal I regions 18, 19 are formed by etching the dielectric layer 330 to form the openings 340. The etching involves two steps, a BHF wet etch followed by anisotropic dry etch, in which steps the dielectric 330 is 40% and 60% etched, respectively. After the contact openings 340 are first formed, a reflow etch step is used to round the tops of the contact openings. Typically, the contact aspect ratio (depth/width) is about 1.8. Then, the metal contact regions 18, 19 are formed in the openings 340 according to a so-called metal (I) process. A variety of processes have been suggested in the prior art for the metal (I) process, such as, the conventional W(tungsten)-CVD plug process, or an Al-based metallization process.
As shown in FIG. 2A, the metal I regions 18, 19 are separated by portions 22 of the semiconductor IC surface 20. The metal I regions 18, 19 which project from the semiconductor IC surface 20, therefore cause the surface of the semiconductor IC 10 to be uneven or non-planar. Next, as shown in FIG. 2B, the semiconductor IC 10 is placed in a PECVD chamber and a PECVD oxide 24 (referred to as an inter-metal dielectric I or IMD I layer) is formed on the metal I regions 18, 19 and portions 22 of the semiconductor surface 20. As shown, the IMD I layer, by virtue of being formed by a PECVD process, conforms to the uneven semiconductor surface of the IC 10. The surface of the semiconductor IC 10, therefore, is still uneven. To even-off or planarize the surface of the semiconductor IC 10, one or more SOG layers 26 are formed on the IMD I layer 24, as shown in FIG. 2C. An SOG layer is illustratively formed from an organic material such as siloxane. The chemical composition of the SOG layer 26 is SiO(CH).sub.x. The level of organic content effects the ability of the SOG material to fill gaps in the IC surface to make it planar; generally, higher organic content provides for better gap-filling/planarization. As shown, the uppermost SOG layer surface 26 tends to be more even or planar than the semiconductor IC surface on which the SOG layer 26 was formed. Optionally, the SOG layer(s) 26 may be etched back somewhat to improve the planarity. Next, as shown in FIG. 2D, in a PECVD chamber, a second PECVD IMD II layer 28 is formed on the SOG layer(s) 26. As shown in FIG. 2E, after forming the IMD II layer 28, the IMD I 24/SOG 26/IMD II 28 sandwiched layers are patterned using a photolithographic process to form vias 30 (passages that extend perpendicularly to the view depicted in FIG. 2D). The vias 30, 31 are formed in the vicinity of the metal I regions 18, 19, respectively. Thereafter, as shown in FIG. 2F, the vias are filled with metal II regions 32, 33. The metal II regions 32 interconnect each metal I region 18 and the metal II regions 33 interconnect each metal I region 19.
A problem with the above inter-dielectric process relates to the use of the SOG layer(s) 26. See C. K. Wang, L. M. Liu, H. C. Cheng, H. C. Huang & M. S. Lin, A Study of Plasma Treatments on Siloxane SOG, VMIC CONF., 1994 ISMIC-103/94/101, June 7-8, p. 101-108; M. Matsura, Y. Ii, K. Shibata, Y. Hayashide & H. Kotani, An Advanced Interlayer Dielectric System with Partially Converted Organic SOG by Using Plasma Treatment, VMIC CONF., 1993 ISMIC-102/93/0113, June 8-9, p.113-15; and S. Itoh, Y. Homma, E. Sasaki, S. Uchimura & H. Morishima, Application of Surface Reformed Thick Spin-on-Glass to MOS Device Planarization, J. ELECTROCHEM. SOC., vol. 137, no. 4, April 1990, p. 1212-18. In forming the vias in the IMD I 24/SOG 26/IMD II 28 sandwiched layers, a photoresist layer is applied to the surface of the IMD II layer 28 and exposed through a mask to pattern the photoresist layer. The unexposed portions of the photoresist are removed and an etchant is introduced to etch vias through the portions of the IMD I 24/SOG 26/IMD II 28 sandwiched layers not protected by exposed photoresist. The exposed photoresist is then removed. When the exposed photoresist is removed, a portion of the SOG layer on the sidewalls of the vias is exposed to O.sub.2 plasma. At such time, alkyl can decompose in the SOG producing moisture. The moisture, in turn, can cause an outgassing effect that can poison the via. The SOG layer can furthermore retrogress or shrink thereby introducing high shear stresses to the surface between the SOG layer 26 and the IMD II layer 28. This can result in cracking of the IMD I 24/SOG 26/IMD II 28 sandwiched layers.
Prior art remedies to this problem are directed to treating the SOG layer to degas/dehydrate/reduce the organic content of the SOG layer prior to adding the IMD II layer. For instance, according to some prior art processes, after forming the SOG layer(s) but before forming the IMD II layer, the semiconductor surface 20 is placed in a furnace and cured at 400.degree.-600.degree. C. S. Ito, Y. Homma, E. Sasaki, S. Uchimura & H. Morishima, Application of Surface Reformed Thick Spin-on-Glass to MOS Device Planarization, J. ELECTROCHEM. SOC., vol. 137, no. 4, April 1990, p. 1212-18 compares the curing of SOG layers in O.sub.2 and N.sub.2. M. Matsuura, Y. Ii, K. Shibata, Y. Hayashide & H. Kotani, An Advanced Interlayer Dielectric System with Partially Converted Organic SOG by Using Plasma Treatment, VMIC CONF., 1993 ISMIC-102/93/0113 teaches to treat the SOG layer(s) with O.sub.2 plasma at 400.degree. C. for 15 seconds to decompose the alkyl of the organic SOG and then to treat the SOG layer with N.sub.2 plasma at 400.degree. C. for one minute. However, the treatment with O.sub.2 plasma can result in high moisture absorption. C. K. Wang, L. M. Liu, H. C. Cheng, H. C. Huang & M. S. Lin, A Study of Plasma Treatments on Siloxane SOG, VMIC CONF., 1994 ISMIC-103/94/101, June 7-8, p. 101-108 teaches to treat the SOG layer(s) with N.sub.2 O or Ar plasma. However, as shown in FIG. 6 of this reference, severe cracks tend to occur using this process.
In each of these processes, the semiconductor IC must be treated ex-situ, i.e., in a different chamber from that used to form the SOG or IMD II layers. Stated another way, to treat the SOG layer according to the prior art, the semiconductor IC must be removed from a first chamber, placed in a second specialized chamber for treatment and then removed for placement in the PECVD chamber. As acknowledged by the prior art, this can cause cracks in the treated SOG layer when the SOG layer is exposed to the ambient environment (i.e., ambient temperature, pressure, etc.) as is required for moving the semiconductor to the PECVD chamber for forming the IIMD II layer. Second, none of the prior art references addresses the issue of delamination which occurs because of poor adhesion between the treated SOG layer and the IMD II layer.
It is therefore an object of the present invention to overcome the disadvantages of the prior art.